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GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver
September 2001 Revised July 2002
GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP36T612 is an 36-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s Partitioned as two 18-Bit transceivers with individual latch timing and output control s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port source/sink -24mA/+24mA s B Port sink +50mA s For more information see AN-5026, Using BGA Packages
Ordering Code:
Order Number GTLP36T612G (Note 1)(Note 2) Package Number BGA114A Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code "G" indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2002 Fairchild Semiconductor Corporation
DS500590
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GTLP36T612
Truth Table
(Note 3) Inputs CEAB OEAB LEAB CLKAB A X L L X X L L H L L L L L L X L L H H L L X H L X X X Output B Z Latched storage of A data Transparent Mode
Pin Descriptions
Pin Names OEAB OEBA CEAB CEBA LEAB L H L H Clocked storage of A data LEBA VREF CLKAB CLKBA A1-A18 B1-B18 Description A-to-B Output Enable (Active LOW) (LVTTL Level) B-to-A Output Enable (Active LOW) (LVTTL Level) A-to-B Clock/LE Enable (Active LOW) (LVTTL Level) B-to-A Clock/LE Enable (Active LOW) (LVTTL Level) A-to-B Latch Enable (Transparent HIGH) (LVTTL Level) B-to-A Latch Enable (Transparent HIGH) (LVTTL Level) GTLP Input Threshold Reference Voltage A-to-B Clock (LVTTL Level) B-to-A Clock (LVTTL Level) A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B Open Drain Outputs
X B0 (Note 4) X B0 (Note 5) L H L H

H
L
L
X
X B0 (Note 5) Clock inhibit
Note 3: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. Note 4: Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Note 5: Output level before the indicated steady-state input conditions were established.
Connection Diagram
Pin Assignment for FBGA
FBGA Pin Assignments
Number in front of each pin indicates word. 1 A B C D E F G H J K L M N P R T U V W 2A2 2A4 2A6 2A8 2A10 2A12 2A14 2A16 2A18 2A1 2A3 2A5 2A7 2A9 2A11 2A13 2A15 2A17 2OEAB 2CLKAB 2LEAB VCC GND GND GND VCC 2CEAB VCC GND GND GND VREF 2B2 2B4 2B6 2B8 2B10 2B12 2B14 2B16 2B18 2B1 2B3 2B5 2B7 2B9 2B11 2B13 2B15 2B17 1A2 1A4 1A6 1A8 1A10 1A12 1A14 1A16 1A18 2 1A1 1A3 1A5 1A7 1A9 1A11 1A13 1A15 1A17 3 1LEAB VCC GND GND GND VCC 4 1CEAB VCC GND GND GND VREF 5 1B2 1B4 1B6 1B8 1B10 1B12 1B14 1B16 1B18 6 1B1 1B3 1B5 1B7 1B9 1B11 1B13 1B15 1B17
1OEAB 1CLKAB
1OEBA 1CEBA 1LEBA 1CLKBA
2OEBA 2CEBA 2LEBA 2CLKBA
(Top Thru View)
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GTLP36T612
Functional Description
The GTLP36T612 is an 36-bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) and the output enables (OEAB and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively. For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is similar except that CEBA, OEBA, LEBA, and CLKBA are used.
Logic Diagram
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GTLP36T612
Absolute Maximum Ratings(Note 6)
Supply Voltage (VCC ) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 7) DC Output Sink Current into A Port IOL DC Output Source Current from A Port IOH DC Output Sink Current into B Port in the LOW State, IOL DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC ESD Performance Storage Temperature (TSTG) 100 mA 48 mA
-0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5V to VCC + 0.5V
Recommended Operating Conditions (Note 8)
Supply Voltage VCC /VCCQ Bus Termination Voltage (VTT) GTLP VREF Input Voltage (VI) on A Port and Control Pins on B Port HIGH Level Output Current (IOH) A Port LOW Level Output Current (IOL) A Port 0.0V to 3.45V 0.0V to 3.45V 1.47V to 1.53V 0.98V to 1.02V 3.15V to 3.45V
-48 mA
-24 mA +24 mA +50 mA -40C to +85C
-50 mA -50 mA +50 mA >2000V -65C to +150C
B Port Operating Temperature (TA)
Note 6: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions in not implied. Note 7: IO Absolute Maximum Rating must be observed. Note 8: Unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL VREF VIK VOH A Port B Port Others B Port Others GTLP (Note 10) VCC = 3.15V VCC = 3.15V VOL A Port B Port II Control Pins A Port B Port IOFF II(hold) IOZH IOZL ICC (VCC/VCCQ) II = -18 mA VCC -0.2 2.4 2.0 0.2 0.5 0.40 0.55 5 -10 10 5 -5 30 75 -75 10 5 -10 -5 60 60 60 80 80 90 mA V V A A A A A A A V IOH = -8 mA IOH = -24mA VCC, VCCQ = Min to Max (Note 11) IOL = 100 A VCC = 3.15V VCC = 3.15V VCC = Min to Max (Note 11) VCC = 3.45V VCC = 3.45V IOL = 24mA IOL = 40 mA IOL = 50 mA VI = 3.45V or 0V VI = 0V VI = 3.45 VI = VCC VI = 0 A Port and Control Pins VCC = 0 A Port A Port B Port A Port B Port A or B Ports VCC = 3.45V IO = 0 VI = VCC or GND VCC = 3.45V VCC = 3.15V VCC = 3.45V VI or VO = 0 to 3.45V VI = 0.8V VI = 2.0V VO = 3.45 VO = 3.45V VO = 0V VO = 0V Outputs HIGH Outputs LOW Outputs Disabled VCC, VCCQ = Min to Max (Note 11) IOH = -100 A 1.0 -1.2 Test Conditions Min VREF +0.05 2.0 0.0 VREF - 0.05 0.8 Typ (Note 9) VTT Max Units V V V V
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GTLP36T612
DC Electrical Characteristics
Symbol ICC (Note 12) Ci A Port and Control Pins Control Pins A Port B Port VCC = 3.45V,
(Continued)
Min Typ (Note 9) 2 6 7.5 9.0 pF Max
Test Conditions One Input at 2.7V VI = VCC or 0 VI = VCC or 0 VI = VCC or 0
Units mA
A or Control Inputs at VCC or GND
Note 9: All typical values are at VCC = 3.3V, VCCQ = 3.3V, and TA = 25C. Note 10: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and Rterm can be adjusted beyond the recommended operating conditions to accommodate backplane impedances other than 50, but must remain within the boundaries of the DC Absolute Maximum ratings. Similarly VREF can be adjusted to optimize noise margin. Note 11: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 12: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol fMAX tWIDTH tSU Maximum Clock Frequency Pulse Duration Setup Time LEAB or LEBA HIGH CLKAB or CLKBA HIGH or LOW A before CLKAB B before CLKBA A before LEAB B before LEBA CEAB before CLKAB CEBA before CLKBA tHOLD Hold Time A after CLKAB B after CLKBA A after LEAB B after LEBA CEAB after CLKAB CEBA after CLKBA Test Conditions Min 175 3.0 3.0 1.1 3.0 1.1 2.7 1.2 1.4 0.0 0.0 0.8 0.0 1.0 1.9 ns ns Max Unit MHz ns
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GTLP36T612
AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tRISE tFALL tPLH tPHL tPLH tPHL tPLH tPHL tPZH, tPZL tPHZ, tPLZ
Note 13: All typical values are at VCC = 3.3V, and TA = 25C.
From (Input) A LEAB CLKAB
To (Output) B B B
Min 2.1 1.0 2.2 1.0 2.2 1.0
Typ (Note 13) 4.1 2.7 4.2 2.4 4.4 2.5 3.8 2.6 3.1 2.1
Max 6.3 4.4 6.3 4.2 6.5 4.4 5.6 4.3
Unit ns ns ns
OEAB
B
2.0 1.0
ns ns
Transition Time, B Outputs (20% to 80%) Transition Time, B Outputs (20% to 80%) B LEBA CLKBA A A A 1.8 1.8 0.3 0.4 0.5 0.6 OEBA A 0.3 0.3
3.8 3.8 2.2 2.4 2.4 2.6 2.7 2.5
5.8 5.8 4.6 4.6 4.6 4.6 5.2 5.2
ns ns ns
ns
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GTLP36T612
Test Circuits and Timing Waveforms
Test Circuit for A Outputs Test Circuit for B Outputs
Test tPLZ/tPZL
S 6V
Note B: For B Port, CL = 30 pF is used for worst case.
tPLH/tPHL Open tPHZ/tPZH GND
Note A: CL includes probes and Jig capacitance.
Voltage Waveform - Propagation Delay Times
Voltage Waveform - Setup and Hold Times
Voltage Waveform - Pulse Width
Voltage Waveform - Enable and Disable times
Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output. Output Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output.
Input and Measure Conditions A or LVTTL Pins VinHIGH VinLOW VM VX VY 3.0 0.0 1.5 VOL + 0.3V VOH - 0.3V B or GTLP Pins 1.5 0.0 1.0 N/A N/A
All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), Z O = 50. The outputs are measured one at a time with one transition per measurement.
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GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver
Physical Dimensions inches (millimeters) unless otherwise noted
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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